View AD9655-125EBZ_9111726.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

dual , 1 6 - bit, 125 msps serial lvds, 1.8 v analog - to - digital converter data sheet ad9655 features 1.8 v supply operation low p ow er: approximately 150 mw / cha nne l at 125 msps , 2 v p - p in put range (typical) snr /sfdr at 69.5 mhz 77.5 dbfs/88 dbc, 2.0 v p - p input range (typical) 79.3 dbfs/84 dbc, 2.8 v p - p input range (typical) linearity dnl = 0.7 lsb; inl = 4.0 lsb (typical , 2.0 v p - p input spa n ) dnl = 0.7 lsb; inl = 3.4 lsb (typical , 2.8 v p - p input spa n ) serial lvds , two data lanes per adc channel 5 0 0 mhz full power analog bandwidth serial port control full chip and individual channel power - down modes flexible bit orientation built - in and custom digital test pattern generation c lock divider programmable output clock and data alignment standby mode applications communications diversity radio systems multimode digital receivers gsm, edge, w - c d m a, lt e, cdma2000, wimax, td - scdma i/q demodulation systems smart antenna systems broadband data applications battery - powered instruments hand held scope meters portable medi cal imaging and u ltrasound radar/lidar g eneral description the ad9655 is a dual, 16 - bit, 125 msps analog - to - digital con verter (adc) with an on - chip sample - and - hold circuit designed for low cost, low power, small size, and ease of use. the product operates at a conversion rate of up to 125 msps and is optimized for outstanding dynamic performance and low power in applicatio ns where a small package size is critical. the adc requires a single 1.8 v power supply and an lvpecl - / cmos - /lvds - compatible sample rate clock for full performance operation. external reference or driver components are not required for many applications. the adc automatically multiplies the sample rate clock for the appropriate lvds serial data rate. a data clock output (dco) fo r capturing data on the output and a frame clock output (fco) for signaling a new output byte are provided. functional block dia g ram ad9655 16 vina+ avdd drvdd 16 16 vinb+ vinb? 16 vina? vcm agnd d0a+ d0a? d1a+ d1a? d0b+ d0b? d1b+ d1b? dco+ dco? fco+ fco? 16-bit pipeline adc 16-bit pipeline adc pll, serializer and ddr lvds drivers serial port interface 1 to 8 clock divider sclk/ dfs sdio/ pdwn csb clk+ clk? reference 12737-001 figure 1. individual channel power - down is supported . the ad9655 typically consumes less than 2 mw in serial port interface ( spi ) power - dow n mode . the available digital test pat - terns include built - in deterministic and pseudorandom patterns, along with custom user - defined test patterns entered via the spi . the ad9655 is available in a n rohs - compliant, 32- lead lfcsp. it is specified over the industrial temperature range of ?40c to +85c. this device is protected by a u.s. patent. product highlights 1. small f ootprint. two adcs are contained in a small, space - saving package. 2. pin compatib le. the ad9655 is pin compatible to the ad9645 14- bit and ad963 5 12- bit dual adc s. 3. ease of u se. a dco operates at frequencies of up to 500 mhz and supports double data rate (ddr) operation. 4. user f lexibility. the spi control offers a wide range of flexible features to meet specific system requirements. rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 analog devices, inc. all rights reserved. technical support www.analog.com
ad9655* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad9655 evaluation board documentation data sheet ? ad9655: dual, 16-bit, 125 msps serial lvds, 1.8 v analog- to-digital converter data sheet user guides ? ad9655/ad9645/ad9635 evaluation documentation tools and simulations ? ad9655 s parameter design resources ? ad9655 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad9655 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad9655 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 dc specificati ons ......................................................................... 3 ac specifications .......................................................................... 5 digital specifications ................................................................... 7 switching specifications .............................................................. 8 timing specifications .................................................................. 8 absolute maximum ratings .......................................................... 10 thermal resistance .................................................................... 10 esd caution ................................................................................ 10 pin configuratio n and function descriptions ........................... 11 typical performance characteristics ........................................... 12 v ref = 1.0 v ................................................................................. 12 v ref = 1.4 v ................................................................................. 15 equivalent circu its ......................................................................... 18 theory of operation ...................................................................... 19 analog input considerations .................................................... 19 voltage reference ....................................................................... 20 clock input considerations ...................................................... 22 power dissipation and power - down mode ........................... 23 digital outputs and timing ..................................................... 24 ou tput test modes ..................................................................... 27 serial port interface (spi) .............................................................. 28 configuration using the spi ..................................................... 28 hardware interface ..................................................................... 29 configurat ion without the spi ................................................ 29 spi accessible features .............................................................. 29 memory map .................................................................................. 30 reading the memory map register table ............................... 30 memory map register table ..................................................... 31 memory map register descriptions ........................................ 34 applications information .............................................................. 36 design guidelines ...................................................................... 36 power and ground guidelines ................................................. 36 clock stability considerations ................................................. 36 exposed pad thermal heat slug recommendations ............ 36 vcm ............................................................................................. 36 reference bypassing ................................................................... 36 spi port ........................................................................................ 36 outline dimensions ....................................................................... 37 ordering guide .......................................................................... 37 revision history 1 / 15 revision 0: initial version rev. 0 | page 2 of 37
data sheet ad9655 specifications dc s peci fications avdd = 1.8 v, drv dd = 1.8 v, 2 v p - p full - scale differential input mode , internal reference voltage (v ref ) = 1.0 v , input amplitude ( a in ) = ?1.0 dbfs, 125 msps, unless otherwise note d. table 1 . parameter 1 temp erature min typ max unit resolution 16 bits accuracy no missing codes full guaranteed 2 offset error 25c 0.2 % fsr offset matching 25c 0.1 % fsr gain error 25c 3.4 % fsr gain matching 25c 0.4 % fsr differential nonlinearity (dnl) 25c 0.7 lsb integral nonlinearity (inl) 25c 4.0 lsb temperature drift gain error full ? 23 ppm/ c offset error full 0.9 ppm/ c internal voltage r e ference output voltage (1 v mode) 25c 1.0 v load regulation at 1.0 ma (v ref = 1 v) 25c 2 .9 mv input resistance 25c 7.5 k ? input - referred noise v ref = 1.0 v 25c 2.7 lsb rms analog inputs differential input voltage (v ref = 1 v) full 2 v p -p common - mode voltage full 0.9 v common - mode range 25c 0.5 1.2 v differential input resistance 25c 1.9 k? differential input capacitance 25c 6.6 pf power supply avdd full 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 v i avdd 3 25c 93 ma i drvdd (ansi - 644 mode) 3 25c 7 3 ma i drvdd (reduced range mode) 3 25c 62 ma total power consumption sine wave input ( two channels , including output drivers ansi - 644 mode) 25c 299 mw sine wave input (two channels, including output drivers reduced range mode) 25c 279 mw power - down 25c 2 mw standby 4 25c 142 mw 1 see the an - 835 application note , understan ding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 no missing codes guaranteed if registe r 0x18 = 0x04 (default, no digital scaling of the output). 3 measured with a low input frequency, ? 1 dbfs sine wave on both chan nels, ddr operation , and two - lane operation. 4 standby mode c an be controlled via the spi. rev. 0 | page 3 of 37
ad9655 data sheet av d d = 1.8 v, drvdd = 1.8 v, 2 .8 v p - p full - scale differential input mode , v ref = 1. 4 v, a in = ?1.0 dbfs, 125 msps, unless otherwise noted. table 2 . parameter 1 temp erature min typ max unit resolution 16 bits accuracy no missing codes full guaranteed 2 offset error full ? 0.12 + 0. 2 + 0.48 % fsr offset matching full ? 0.2 + 0. 1 + 0.33 % fsr gain error full ? 2.4 + 2.8 + 8.2 % fsr gain matching full ? 1.2 + 0.4 + 1.9 % fsr d ifferential nonlinearity (d nl) full ? 0.99 + 1.43 lsb 25c 0.7 lsb integral nonlinearity ( inl ) full 8.5 + 8.5 lsb 25c 3.4 lsb temperature drift gain error full 66 ppm/ c offset error full 0.9 ppm/ c internal voltage reference output voltage (1 .4 v mode) full 1.37 1. 38 1.41 v load regulation at 1.0 ma (v ref = 1 .4 v) 25c 186 mv input resistance 25c 7.5 k input - referred noise v ref = 1. 4 v 25c 2 lsb rms analog inputs differential input voltage (v ref = 1 .4 v) full 2 .8 v p -p common - mode voltage full 0.9 v common - mode range 25c 0.7 1. 0 v differential input resistance 25c 1.9 k differential input capacitance 25c 6.6 pf power supply avdd full 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 v i avdd 3 full 101 111 ma i drvdd (ansi - 644 mode) 3 full 73 79 ma i drvdd (reduced range mode) 3 full 62 68 ma total power consumption sine wave input ( two channels , including output drivers ansi - 644 mode) full 313 342 mw sine wave input ( two channels , including output drivers reduced range mode) full 293 322 mw power - down full 2 4 mw standby 4 full 155 172 mw 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 no missing codes guaranteed if register 0x18 = 0x04 (default, no digital scaling of the output) . 3 measured with a low input f requency, ? 1 dbfs sine wave on both channels, ddr operation , and two - lane operation. 4 standby mode c an be controlled via the spi. rev. 0 | page 4 of 37
data sheet ad9655 ac specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p full - scale differential input mode , v ref = 1.0 v, a in = ?1.0 dbfs, 125 msps, unless otherwise noted. table 3 . parameter 1 temperature min typ max unit signal - to - noise ratio (snr) f in = 9.7 mhz 25c 77.9 dbfs f in = 19.7 mhz 25c 77.9 dbfs f in = 69.5 mhz 25c 77. 5 dbfs f in = 1 00 .5 mhz 25c 76.6 dbfs f in = 139.5 mhz 25c 75.6 dbfs f in = 301 mhz 25c 71.0 dbfs signal - to - noise - and - distortion ratio (sinad) f in = 9.7 mhz 25c 77.5 dbfs f in = 19.7 mhz 25c 77.1 dbfs f in = 69.5 mhz 25c 77.1 dbfs f in = 1 00 .5 mhz 25c 76.5 dbfs f in = 139.5 mhz 25c 75.2 dbfs f in = 301 mhz 25c 68.0 dbfs effective number of bits (enob) f in = 9.7 mhz 25c 12.6 bits f in = 19.7 mhz 25c 12.5 bits f in = 69.5 mhz 25c 12.5 bits f in = 1 00 .5 mhz 25c 12.4 bits f in = 139.5 mhz 25c 12.2 bits f in = 301 mhz 25c 11 bits spurious - free dynamic range (sfdr) f in = 9.7 mhz 25c 88 dbc f in = 19.7 mhz 25c 86 dbc f in = 69.5 mhz 25c 88 dbc f in = 1 00 .5 mhz 25c 91 dbc f in = 139.5 mhz 25c 85 dbc f in = 301 mhz 25c 70 dbc worst harmonic (second or third) f in = 9.7 mhz 25c ? 88 dbc f in = 19.7 mhz 25c ? 86 dbc f in = 69.5 mhz 25c ? 88 dbc f in = 1 00 .5 mhz 25c ? 91 dbc f in = 139.5 mhz 25c ? 85 dbc f in = 301 mhz 25c ? 70 dbc worst other (excluding second or third harmonic ) f in = 9.7 mhz 25c ? 95 dbc f in = 19.7 mhz 25c ? 99 dbc f in = 69.5 mhz 25c 92 dbc f in = 1 00 .5 mhz 25c 91 dbc f in = 139.5 mhz 25c 89 dbc f in = 301 mhz 25c 80 dbc two - tone intermodulation distortion (imd) ? a in1 and a in2 = 7.0 dbfs f in1 = 100. 1 mhz, f in2 = 102. 1 mhz 25c 90 dbc crosstalk 2 25c 104 db crosstalk (overrange condition) 3 25c 100 db analog input bandwidth, full power 25c 500 mhz 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 crosstalk is measured at 69.5 mhz with ?1.0 dbfs analog input on one channel and no input on the adjacent channel. measurements are taken using a less dense board to demonstrate the ad9655 crosstalk performance, not board limitations. 3 o verrange condition is specifie d as being 3 db above the full - scale input range. rev. 0 | page 5 of 37
ad9655 data sheet av dd = 1.8 v, drvdd = 1.8 v, 2 .8 v p - p full - scale differential input mode , v ref = 1. 4 v, a in = ?1.0 dbfs, 125 msps, unless otherwise noted. table 4 . parameter 1 temperature min typ max unit signal - to - noise ratio (snr) f in = 9.7 mhz 25c 79.6 dbfs f in = 19.7 mhz 25c 79.4 dbfs f in = 69.5 mhz full 78.0 79.3 dbfs f in = 1 00 .5 mhz 25c 78.0 dbfs f in = 139.5 mhz 25c 76.5 dbfs f in = 301 mhz 25c 55.0 dbfs signal - to - noise - and - distortion ratio (sinad) f in = 9.7 mhz 25c 79.1 dbfs f in = 19.7 mhz 25c 78.3 dbfs f in = 69.5 mhz full 77.2 77. 8 dbfs f in = 1 00 .5 mhz 25c 77.0 dbfs f in = 139.5 mhz 25c 75.8 dbfs f in = 301 mhz 25c 54.8 dbfs effective number of bits (enob) f in = 9.7 mhz 25c 12.8 bits f in = 19.7 mhz 25c 12.7 bits f in = 69.5 mhz full 12.5 12.6 bits f in = 1 00 .5 mhz 25c 12.5 bits f in = 139.5 mhz 25c 12.3 bits f in = 301 mhz 25c 8.8 bits spurious - free dynamic range (sfdr) f in = 9.7 mhz 25c 88 dbc f in = 19.7 mhz 25c 85 dbc f in = 69.5 mhz full 80 8 4 dbc f in = 1 00 .5 mhz 25c 83 dbc f in = 139.5 mhz 25c 82 dbc f in = 301 mhz 25c 68 dbc worst harmonic (second or third) f in = 9.7 mhz 25c ? 88 dbc f in = 19.7 mhz 25c ? 85 dbc f in = 69.5 mhz full ? 84 ? 8 0 dbc f in = 1 00 .5 mhz 25c ? 83 dbc f in = 139.5 mhz 25c ? 82 dbc f in = 301 mhz 25c ? 68 dbc worst other (excluding second or third harmonic ) f in = 9.7 mhz 25c ? 97 dbc f in = 19.7 mhz 25c ? 98 dbc f in = 69.5 mhz full 93 85 dbc f in = 1 00 .5 mhz 25c 91 dbc f in = 139.5 mhz 25c 89 dbc f in = 301 mhz 25c 72 dbc two - tone intermodulation distortion (imd) ? a in1 and a in2 = 7.0 dbfs f in1 = 100. 1 mhz, f in2 = 102. 1 mhz 25c 85 dbc crosstalk 2 25c 104 db crosstalk (overrange condition) 3 25c 103 db analog input bandwidth, full power 25c 500 mhz 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 crosstalk is measured at 69.5 mhz with ?1.0 dbfs analog input on one channel and no input on the adjacent channel. measurements are taken using a less dense board to demonstrate ad9655 crosstalk performance, not board limitat ions. 3 o verrange condition is speci fied as being 3 db above the full - scale input range. rev. 0 | page 6 of 37
data sheet ad9655 digital specificatio ns avdd = 1.8 v and drvdd = 1.8 v, unless otherwise noted. table 5 . parameter 1 temp erature min typ max unit clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl differential input voltage 2 full 0.2 3.6 v p -p input voltage range full agnd ? 0. 2 avdd + 0.2 v input common - mode voltage full 0.9 v input resistance (differential) 25c 15 k ? input capacitance 25c 4 pf logic inputs ( sclk /dfs ) logic 1 voltage full 1.2 avdd + 0. 2 v logic 0 voltage full 0 0.8 v input resistance 25c 30 k ? input capacitance 25c 2 pf logic input (csb) logic 1 voltage full 1.2 avdd + 0.2 v logic 0 voltage full 0 0.8 v input resistance 25c 26 k ? input capacitance 25c 2 pf logic input (sdio /pdwn ) logic 1 voltage full 1.2 avdd + 0. 2 v logic 0 voltage full 0 0.8 v input resistance 25c 26 k ? input capacitance 25c 5 pf logic output (sdio /pdwn ) 3 logic 1 voltage (i oh = 800 a) full 1.79 v logic 0 voltage (i ol = 50 a) full 0.05 v digital outputs (d 0 x , d 1 x ), ansi - 644 logic compliance lvds differential output voltage (v od ) full 298 350 400 mv output offset voltage (v os ) full 1.15 1.22 1.30 v output coding (default) two s c omplement digital outputs (d0 x , d1 x ), low power, reduced signal option logic compliance lvds differential output voltage (v od ) full 170 200 231 mv output offset voltage (v os ) full 1.15 1.22 1.30 v output coding (default) twos c omplement 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 s pecified for lvds and lvpecl only. 3 s pecified for 13 sdio/pdwn pins sharing the sam e connection. rev. 0 | page 7 of 37
ad9655 data sheet switching specificat ions avdd = 1.8 v and drvdd = 1.8 v, u nless otherwise noted. table 6 . parameter 1 , 2 temp erature min typ max unit clock 3 input clock rate full 20 1000 mhz conversion rate full 20 125 msps clock pulse width high (t eh ) full 4.00 ns clock pulse width low (t el ) full 4.00 ns output parameters 3 propagation delay (t pd ) 4 full (t sample / 4 ) + 5 (t sample / 4 ) + 6.1 (t sample / 4 ) + 7 ns rise time (t r ) 5 (20% to 80%) full 170 ps fall time (t f ) 5 (20% to 80%) full 160 ps fco propagation delay (t fco ) 4 full (t sample / 4 ) + 5 (t sample / 4 ) + 6.1 (t sample / 4 ) + 7 ns dco propagation delay (t cpd ) 4 full t fco + (t sample /1 6 ) + 0.2 ns d co to d ata delay (t data ) 4 , 6 full (t sample /1 6 ) ? 5 00 (t sample /1 6 ) + 1 00 ps f co to d co delay (t frame ) 4 , 7 full ( t sample /16) + 1 0 (t sample /16) + 330 ps da ta to data sk ew full 37 80 ps wake - up time (standby) 25c 250 ns wake - up time (power- down) 8 25c 250 m s pipeline latency full 16 clock cycles aperture aperture delay (t a ) 9 25c 1 ns aperture uncertainty (jitter , t j 5 , 9 ) 25c 80 f s rms out - of - range recovery time 25c 1 c lock cycles 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 measured on standard fr - 4 material. 3 the output parameters c an be adjusted via the spi. the conversion rate is the clock rate after the divider. valid for 2 - lane operation. 4 t sample = t eh + t el = 1/f s . t cpd , t data and t frame are adjus table with spi register 0x16. 5 this term does not appear in the timing diagrams section, which includes figure 2 and figure 3 . 6 t data is the time from dco r ise or fall to output data rise or fall . 7 t frame is the time from fco rise to dco rise . 8 wake - up time from power - do wn is defined as the time required to return to normal operation from spi power - down mode. the value of 250 ms assumes a sample rate of 125 m sp s . about 31 10 6 sample clock cycles are required. 9 t a and t j are with register 0x09 = 0x04 (default, duty cycle stabilizer and clock divi der are bypassed) . timing specification s table 7 . parameter description limit unit spi timing requirements see figure 68 , unless otherwise noted t ds setup time between the data and the rising edge of sclk 4 ns min t dh hold time between the data and the rising edge of sclk 2 ns min t clk period of the sclk 40 ns min t s setup time between csb and sclk 2 ns min t h hold time between csb and sclk 2 ns min t high sclk pulse width high 10 ns min t low sclk pulse width low 10 ns min t en_sdio 1 time required for the sdio pin to switch from an input to an output relative to the sclk falling edge 10 ns min t dis_sdio 1 time required for the sdio pin to switch from an output to an input relative to the s clk rising edge 10 ns min 1 this parameter is not shown in figure 68. rev. 0 | page 8 of 37
data sheet ad9655 timing diagrams d0a? d0a+ d1a? d1a+ fco? bytewise mode fco+ d0a? d0a+ d1a? d1a+ fco? dco? dco+ dco+ clk+ vinx clk? dco? fco+ bitwise mode sdr ddr msb n ? 17 d14 n ? 17 d13 n ? 17 d12 n ? 17 d11 n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 msb n ? 16 d14 n ? 16 d13 n ? 16 d12 n ? 16 d11 n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 17 d06 n ? 17 d05 n ? 17 d04 n ? 17 d03 n ? 17 d2 n ? 17 d01 n ? 17 lsb n ? 17 d07 n ? 16 d06 n ? 16 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 msb n ? 17 d13 n ? 17 d11 n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 msb n ? 16 d13 n ? 16 d11 n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 d14 n ? 17 d12 n ? 17 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 d14 n ? 16 d12 n ? 16 d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 t a t data t eh t fco t frame t pd t cpd t el n ? 1 n n + 1 12737-002 figure 2. 16 - bit ddr/s ingle data rate (s dr ) , two - lane, 1 frame mode (default) d0x? d0x+ fco? dco+ clk+ vinx clk? dco? fco+ d14 n ? 17 msb n ? 17 d13 n ? 17 d12 n ? 17 d11 n ? 17 d10 n ? 17 d9 n ? 17 d8 n ? 17 d7 n ? 17 d6 n ? 17 d5 n ? 17 d4 n ? 17 d3 n ? 17 d2 n ? 17 d1 n ? 17 lsb n ? 17 msb n ? 16 d14 n ? 16 d13 n ? 16 t a t data t eh t fco t frame t pd t cpd t el n ? 1 n 12737-003 figure 3 . wordw ise ddr, one - lane, 1 frame, 16 - bit output mode rev. 0 | page 9 of 37
ad9655 data sheet absolute maximum rat ings table 8 . parameter rating electrical avdd to agnd ? 0.3 v to +2.0 v drvdd to agnd ? 0.3 v to +2.0 v digital outputs (d0x, d1x , dco , fco ) to agnd ? 0.3 v to +2.0 v clk+, clk? to agnd ? 0.3 v to +2.0 v vin x+ , vin x ? to agnd ? 0.3 v to +2.0 v sclk /d fs , sdio / pdwn , csb to agnd ? 0.3 v to +2.0 v rbias to agnd ? 0.3 v to +2.0 v vref to agnd ? 0.3 v to +2.0 v v cm to agnd ? 0.3 v to +2.0 v environmental operating temperature range (ambient) ? 40 c to +85c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c storage temperature range (ambient) ? 65c to +150 c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance the exposed pad is the only groun d connection for the chip. the exposed pad must be soldered to the agnd plane of the circuit board. soldering the exposed pad to the board also increases the reliability of the solder joints and maximizes the thermal capability of the package. table 9 . thermal resistance package type airflow velocity (m/sec) ja 1, 2 jc 1, 3 jb 1, 4 32- lead lfcsp , 5 mm 5 mm 0 37.1 3.1 20.7 0.3 c/w 1.0 32.4 n/a 5 n/a 5 0.5 c/w 2.5 29.1 n/a 5 n/a 5 0.8 c/w 1 per jedec 51 - 7, plus jedec 51 - 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air). 3 per mil - std 883, method 1012.1. 4 per jedec jesd51 - 8 (still air). 5 n/a means not applicable. typical ja is specified for a 4 - layer printed circuit board ( pcb ) with a so lid ground plane. as shown in table 9 , airflow improves heat dissipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces ja . esd caution rev. 0 | page 10 of 37
data sheet ad9655 pin configuration an d function descripti ons 24 avdd 23 rbias 22 vcm 21 vref 20 csb 19 drvdd 18 d0a+ 17 d0a? 1 2 3 4 5 6 7 8 avdd clk+ clk? sdio/pdwn sclk/dfs drvdd d1b? d1b+ 9 10 1 1 12 13 14 15 16 d0b? d0b+ dco? dco+ fco? fco+ d1a? d1a+ 32 31 30 29 28 27 26 25 avdd vinb? vinb+ avdd avdd vina+ vina? avdd ad9655 top view (not to scale) notes 1. the exposed pad is the only ground connection on the chip. it must be soldered to the analog ground of the pcb to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. 12737-004 figure 4 . pin configuration, top view table 10 . pin function descriptions pin no. mnemonic description 0 , exposed pad agnd, exposed pad exposed pad. the exposed pad is the only ground connection on the chip. it must be soldered to the analog ground of the pcb to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits . 1, 24, 25, 28 , 29, 32 avdd 1.8 v supply pin s for the adc core domain. 2, 3 clk+, clk? differential encode cl ock . these pins are pecl - , lvds - , or 1 .8 v cmos - compatible i nputs. 4 sdio/pdwn spi data input/output (sdio). this pin is a b idirectional spi data input/output with a 3 1 k ? internal pull - down resistor. non - spi mode power - down (pdwn). this pin provides s t atic control of chip power - down, and has a 3 1 k ? internal pull - down resistor . 5 sclk/dfs spi clock input in spi mode (sc lk). this pin has a 30 k ? internal pull - down resistor . non - spi mode data format select (dfs). this provides s tatic control of the data output format. this pin has a 30 k ? internal pull - down resistor . pull dfs high for a twos complement output; pull dfs low for an offset binary output. 6, 19 drvdd 1.8 v supply pins for output driver domain. 7, 8 d1b ? , d1b+ channel b lane 1 digital outputs. 9, 10 d0b ? , d0b+ channel b lane 0 digital outputs. 11, 12 dco ? , dco+ data clock outputs. 13, 14 fco ? , fco+ frame clock outputs. 15, 16 d1a ? , d1a+ channel a lane 1 digital outputs. 17, 18 d0a ? , d0a+ channel a lane 0 digital outputs. 20 csb spi chip select. active low enable; this pin has a 15 k? internal pull -up resistor . 21 vref 1.0 v to 1.4 v voltage reference output . b ypass this pin to ground with a 1 .0 f capacitor i n parallel with a 0.1 f capacitor ; this pin internally provides reference voltage to the adc . t his pin c an be disabled via register 0x114 if external v ref is desired. 22 vcm analog output voltage at mid avdd supply. b ypass this pin to ground with a 0.1 f capacitor; this pin c an be used to set the common mode of the analog inputs externally . 23 rbias set s analog current bias. connect this pin to a 10.0 k? (1% tolerance) resistor to ground. 26, 27 v ina?, v ina+ channel a adc analog inputs. 30, 31 vinb+, v inb ? channel b adc analog inputs. rev. 0 | page 11 of 37
ad9655 data sheet typical performance characteristics v ref = 1.0 v 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) 0 10 20 30 40 50 60 a in = ?1dbfs f in = 9.7mhz snr = 77.9dbfs sinad = 76.6dbc sfdr = 89.7dbc 12737-005 figure 5. single - to ne 32k fft with f in = 9.7 mhz, f sample = 125 msps , v ref = 1.0 v 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) 0 10 20 30 40 50 60 a in = ?1dbfs f in = 19.7mhz snr = 78dbfs sinad = 76.1dbc sfdr = 85.9dbc 12737-006 figure 6 . single - tone 32k fft with f in = 19.7 mhz, f sample = 125 msps , v ref = 1.0 v 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) 0 10 20 30 40 50 60 a in = ?1dbfs f in = 69.5mhz snr = 77.5dbfs sinad = 76.0dbc sfdr = 86.6dbc 12737-007 figure 7 . single - tone 32k fft with f in = 69.5 mhz, f sample = 125 msps , v ref = 1.0 v 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) 0 10 20 30 40 50 60 a in = ?1dbfs f in = 100.5mhz snr = 76.6dbfs sinad = 75.5dbc sfdr = 91.1dbc 12737-008 figure 8 . single - tone 32k fft with f in = 1 00.5 mhz, f sample = 125 msps , v ref = 1.0 v 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) 0 10 20 30 40 50 60 a in = ?1dbfs f in = 139.5mhz snr = 75.7dbfs sinad = 74.3dbc sfdr = 85.5dbc 12737-009 figure 9 . single - tone 32k fft with f in = 1 39.5 mhz, f sample = 125 msps , v ref = 1.0 v 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) 0 10 20 30 40 50 60 a in = ?1dbfs f in = 301mhz snr = 71.2dbfs sinad = 67dbc sfdr = 70.3dbc 12737-010 figure 10 . single - tone 32k fft with f in = 301 mhz, f sample = 125 msps , v ref = 1.0 v rev. 0 | page 12 of 37
data sheet ad9655 ?20 0 20 40 60 80 100 120 ?90 ?70 ?50 ?30 ?10 snr, sfdr (db, dbc, and dbfs) input amplitude (dbfs) sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (db) 12737-012 figure 11 . snr, sfdr vs. input amplitude ; f in = 9.7 mhz, f sample = 125 msps , v ref = 1.0 v 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) 0 10 20 30 40 50 60 a in = ?7dbfs f in = 100.1mhz, 102.1mhz imd2 = ?89.6dbc imd3 = ?90.2dbc sfdr = 89.6dbc f 1 ? f 2 f 1 ? f 2 f 1 + v 2 2 f 2 ? f 1 2 f 1 + f 2 f 1 + 2 f 2 12737-013 figure 12 . two - tone 32k fft with f in1 = 100.1 mhz and f in2 = 10 2. 1 mhz, f sample = 125 msps , v ref = 1.0 v ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 ?90 ?70 ?50 ?30 ?80 ?60 ?40 ?20 ?10 sfdr, imd3 (dbc and dbfs) input amplitude (dbfs) ? sfdr (dbc) imd3 (dbc) ? sfdr (dbfs) imd3 (dbfs) 12737-014 figure 13 . two - tone sfdr, imd3 vs. input amplitude ( a in ) with f in1 = 10 0. 1 mhz and f in2 = 10 2. 1 mhz, f sample = 125 msps , v ref = 1.0 v 0 10 20 30 40 50 60 70 80 90 100 500 0 100 200 300 400 snr, sfdr (dbfs and dbc) input frequency (mhz) sfdr (dbc) snr (dbfs) 12737-015 figure 14 . snr, sfdr vs. input frequency (f in ); f sample = 125 msps , v ref = 1.0 v 70 75 80 95 85 90 60 80 ?40 ?20 0 20 40 snr, sfdr (dbfs and dbc) temperature (c) snr (dbfs) sfdr (dbc) 12737-016 figure 15 . snr, sfdr vs. temperature; f in = 9.7 mhz, f sample = 125 msps , v ref = 1.0 v ?5 ?3 ?1 5 1 3 ?4 ?2 0 2 4 inl (lsb) output code 12737-017 0 10000 20000 30000 40000 50000 60000 figure 16 . inl; f in = 9.7 mhz, f sample = 125 msps , v ref = 1.0 v rev. 0 | page 13 of 37
ad9655 data sheet ?0.8 ?0.4 0 0.8 0.4 ?0.6 ?0.2 0.2 0.6 dnl (lsb) output code 12737-018 0 10000 20000 30000 40000 50000 60000 figure 17 . dnl; f in = 9.7 mhz, f sample = 125 msps , v ref = 1.0 v 0 50k 100k 350k 150k 200k 250k 300k n + 14 n + 12 n + 10 n + 8 n + 6 n + 4 n + 2 n n ? 2 n ? 4 n ? 6 n ? 8 n ? 10 n ? 12 n ? 14 number of hits output code 2.7lsb rms 12737-019 figure 18 . input referred noise histogram; f sample = 125 msps , v ref = 1.0 v 0 20 40 100 120 60 80 120 20 40 60 80 100 snr, sfdr (dbfs and dbc) sample rate (msps) sfdr (dbc) snr (dbfs) 12737-021 figure 19 . snr, sfdr vs. sample rate; f in = 9.7 mhz, v ref = 1.0 v 0 20 40 100 120 60 80 120 20 40 60 80 100 snr, sfdr (dbfs and dbc) sample rate (msps) sfdr (dbc) snr (dbfs) 12737-022 figure 20 . snr, sfdr vs. sample rate; f in = 69.5 mhz, v ref = 1.0 v , clock divider = 4 rev. 0 | page 14 of 37
data sheet ad9655 v ref = 1.4 v 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) 0 10 20 30 40 50 60 a in = ?1dbfs f in = 9.7mhz snr = 79.6dbfs sinad = 78dbc sfdr = 88.1dbc 12737-023 figure 21 . single - tone 32k fft with f in = 9.7 mhz, f sample = 125 msps , v ref = 1.4 v 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) 0 10 20 30 40 50 60 a in = ?1dbfs f in = 19.7mhz snr = 79.4dbfs sinad = 77.2dbc sfdr = 85.1dbc 12737-024 figure 22 . single - tone 32k fft with f in = 19.7 mhz, f sample = 125 msps , v ref = 1.4 v 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) 0 10 20 30 40 50 60 a in = ?1dbfs f in = 69.5mhz snr = 79.4dbfs sinad = 76.6dbc sfdr = 83.7dbc 12737-025 figure 23 . single - tone 32k fft with f in = 69.5 mhz, f sample = 125 msps , v ref = 1.4 v 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) 0 10 20 30 40 50 60 a in = ?1dbfs f in = 100.5mhz snr = 78dbfs sinad = 76dbc sfdr = 83.5dbc 12737-026 figure 24 . single - tone 32k fft with f in = 1 00.5 mhz, f sample = 125 msps , v ref = 1.4 v 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) 0 10 20 30 40 50 60 a in = ?1dbfs f in = 139.5mhz snr = 76.6dbfs sinad = 74.8dbc sfdr = 82.4dbc 12737-027 figure 25 . single - tone 32k fft with f in = 1 39.5 mhz, f sample = 125 msps , v ref = 1.4 v 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) 0 10 20 30 40 50 60 a in = ?1dbfs f in = 301mhz snr = 55dbfs sinad = 53.8dbc sfdr = 71.6dbc 12737-028 figure 26 . single - tone 32k fft with f in = 301 mhz, f sample = 125 msps , v ref = 1.4 v rev. 0 | page 15 of 37
ad9655 data sheet sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (db) ?20 0 20 40 60 80 100 120 ?90 ?70 ?50 ?30 ?10 snr, sfdr (db, dbc, and dbfs) input amplitude (dbfs) 12737-030 figure 27 . snr, sfdr vs. input amplitude ; f in = 9.7 mhz, f sample = 125 msps , v ref = 1.4 v 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 amplitude (dbfs) frequency (mhz) 0 10 20 30 40 50 60 a in = ?7dbfs f in = 101.1mhz, 102.1mhz imd2 = ?88.36dbc imd3 = ?85dbc sfdr = 85dbc f 1 ? f 2 2 f 1 ? f 2 f 1 + f 2 2 f 2 ? f 1 2 f 1 + f 2 f 1 + 2 f 2 12737-031 figure 28 . two - tone 32k fft with f in1 = 10 0. 1 mhz and f in2 = 10 2. 1 mhz, f sample = 125 msps , v ref = 1.4 v ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 ?90 ?70 ?50 ?30 ?80 ?60 ?40 ?20 ?10 sfdr, imd3 (dbc and dbfs) input amplitude (dbfs) ? sfdr (dbc) imd3 (dbc) ? sfdr (dbfs) imd3 (dbfs) 12737-032 figure 29 . two - tone sfdr, imd3 vs. input amplitude ( a in ) with f in1 = 10 0. 1 mhz and f in2 = 10 2. 1 mhz, f sample = 125 msps , v ref = 1.4 v 0 10 20 30 40 50 60 70 80 90 100 500 0 100 200 300 400 snr, sfdr (dbfs and dbc) input frequency(mhz) sfdr (dbc) snr (dbfs) 12737-033 figure 30 . snr, sfdr vs. input frequency ( f in ); f sample = 125 msps , v ref = 1.4 v 70 75 80 95 85 90 60 80 ?40 ?20 0 20 40 snr, sfdr (dbfs and dbc) temperature (c) snr (dbfs) sfdr (dbc) 12737-034 figure 31 . snr, sfdr vs. temperature; f in = 9.7 mhz, f sample = 125 msps , v ref = 1.4 v ?4 ?2 0 4 2 ?3 ?1 1 3 inl (lsb) output code 12737-035 0 10000 20000 30000 40000 50000 60000 figure 32 . inl; f in = 9.7 mhz, f sample = 125 msps , v ref = 1.4 v rev. 0 | page 16 of 37
data sheet ad9655 ?0.8 ?0.4 0 0.8 0.4 ?0.6 ?0.2 0.2 0.6 dnl (lsb) output code 12737-036 0 10000 20000 30000 40000 50000 60000 figure 33 . dnl; f in = 9.7 mhz, f sample = 125 msps , v ref = 1.4 v 0 50k 100k 450k 400k 350k 150k 200k 250k 300k n + 9 n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n n ? 1 n ? 2 n ? 3 n ? 4 n ? 5 n ? 6 n ? 7 n ? 8 n ? 9 n ? 10 number of hits output code 2.0lsb rms 12737-037 figure 34 . input referred noise histogram; f sample = 125 msps , v ref = 1.4 v 0 20 40 100 120 60 80 120 20 40 60 80 100 snr, sfdr (dbfs and dbc) sample rate (msps) sfdr (dbc) snr (dbfs) 12737-039 figure 35 . snr, sfdr vs. sample rate; f in = 9.7 mhz , v ref = 1.4 v 0 20 40 100 120 60 80 120 20 40 60 80 100 snr, sfdr (dbfs and dbc) sample rate (msps) sfdr (dbc) snr (dbfs) 12737-040 figure 36 . snr, sfdr vs. sample rate; f in = 69.5 mhz, v ref = 1.4 v , clock divider = 4 rev. 0 | page 17 of 37
ad9655 data sheet rev. 0 | page 18 of 37 equivalent circuits a v dd vinx 12737-041 figure 37. equivalent analog input circuit clk+ clk? 0.9v 15k ? 10 ? 10 ? 15k ? avdd a v dd 12737-042 figure 38. equivalent clock input circuit 31k ? sdio/pdwn 400? dr v dd 12737-043 figure 39. equivalent sdio/pdwn input circuit dr v dd d0x?, d1x? d0x+, d1x+ v v v v 12737-044 figure 40. equivalent digital output circuit 400 ? dr v dd 30k ? sclk/dfs 12737-045 figure 41. equivalent sclk/dfs input circuit rbias a nd vc m 400 ? a v dd 12737-046 figure 42. equivalent rbias and vcm circuit csb 400 ? dr v dd 15k ? 12737-047 figure 43. equivalent csb input circuit vref a v dd 7.5k ? 400 ? 10 ? 12737-048 figure 44. equivalent vref circuit
data sheet ad9655 rev. 0 | page 19 of 37 theory of operation the ad9655 is a multistage, pipelined adc. each stage provides sufficient overlap to correct for flash errors in the preceding stage. the quantized outputs from each stage are combined into a final 16-bit result in the digital correction logic. the serializer transmits this converted data in a 16-bit output. the pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched capacitor dac and an interstage residue amplifier, for example, a multiplying digital-to-analog converter (mdac). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy in each stage facilitates digital correction of flash errors. the last stage consists of a flash adc. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. then, the data is serialized and aligned to the frame and data clocks. analog input considerations the analog input to the ad9655 is a differential switched capacitor circuit designed for processing differential input signals. this circuit can support a wide common-mode range while maintaining excellent performance. by using an input common-mode voltage of midsupply, users can minimize signal dependent errors and achieve optimum performance. ss h c par c sample c sample c par vinx? h ss h v inx+ h 12737-049 figure 45. switched capacitor input circuit the clock signal alternately switches the input circuit between sample mode and hold mode (see figure 45). when the input circuit switches to sample mode, the signal source must be capable of charging the sample capacitors and settling within one half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. a differential capacitor, two single-ended capacitors, or a combination of these capacitors can be placed on the inputs to provide a matching passive network. this ultimately creates a low-pass filter at the input to limit unwanted broadband noise. see the an-742 application note , the an-827 application note , and the analog dialogue article transformer- coupled front-end for wideband a/d converters (volume 39, april 2005) for more information. in general, the precise values depend on the application. input common mode the ad9655 analog inputs are not internally dc-biased. therefore, in ac-coupled applications, the user must provide this bias externally. setting the device so that v cm = avdd/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in figure 46 and figure 47. 10 20 30 40 50 60 70 80 90 100 1.0 1.1 1.2 0.5 0.6 0.7 0.8 0.9 snr, sfdr (dbfs and dbc) v cm (v) 12737-050 sfdr (dbc) snr (dbfs) figure 46. snr, sfdr vs. input common-mode voltage (v cm ), f in = 9.7 mhz, f sample = 125 msps, v ref = 1.0 v 10 20 30 40 50 60 70 80 90 100 0.95 1.00 0.70 0.75 0.80 0.85 0.90 snr, sfdr (dbfs and dbc) v cm (v) 12737-051 sfdr (dbc) snr (dbfs) figure 47. snr, sfdr vs. input common-mode voltage (v cm ), f in = 9.7 mhz, f sample = 125 msps, v ref = 1.4 v
ad9655 data sheet an on - chip, common - mode dc voltage reference is included in the design and is available from the vcm pin. the vcm pin must be bypassed to ground by a 0.1 f capacitor, as described in the applications information section. vcm error vs. load current is shown in figure 48. ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 0 0.5 1.0 1.5 2.0 2.5 vcm error (%) load current (ma) 12737-052 figure 48 . vcm error vs. load current differential input configurations there are several ways to drive the ad9655 either actively or passively. however, optimum performance is achieved by driving the analog inputs differentially. using a differential double b alun configuration to drive the ad9655 provides excellent performance and a flexible interface to the adc for baseband applications (see figure 53 ). for applications where snr is a ke y parameter, differential trans former coupling is the recommended input configuration (see figure 54 ) because the noise performance of most amplifiers is not a dequate to achieve the true performance of the ad9655 . regardless of the configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. it is not recommended to drive the ad9655 inputs single - ended. voltage reference a stable and accurate 1.0 v to 1.4 v dc voltage reference is built into the ad9655 . externally bypass t he vref pin to ground with a low esr, 1.0 f cap acitor in parallel with a low esr, 0.1 f ceramic capacitor. m aximum snr performance is achieved by setting the adc to the largest span in a differential configuration. in the case of the ad9655 , the largest input span available is 2 .8 v p - p , which is achieved by setting v ref to 1.4 v . if th e internal reference of the ad9655 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. figure 49 and figure 50 show how the internal reference voltage is affected by loading. it is recommended that vref not be used to drive the reference voltage of other devices at 1.4 v. figure 51 and figure 52 show the typical drift characteristics of the internal reference. the interna l buffer generates the positive and negative full - scale references for the adc core. a digital reset using register 0x08 must follow any programmatic change in internal analo g v ref . ?60 ?40 ?50 ?30 ?20 ?10 0 2.0 2.5 0 0.5 1.0 1.5 v ref error (%) load current (ma) internal v ref = 1v 12737-053 figure 49 . v ref error vs. load current , v ref = 1.0 v ?70 ?60 ?40 ?50 ?30 ?20 ?10 0 2.0 2.5 0 0.5 1.0 1.5 v ref error (%) load current (ma) internal v ref = 1.4v 12737-054 figure 50 . v ref error vs. load current , v ref = 1.4 v ?0.006 ?0.008 ?0.002 ?0.004 0 0.002 0.004 40 60 80 ?40 ?20 0 20 v ref error (v) temperature (c) internal v ref = 1v 12737-055 figure 51 . typical v ref drift , v ref = 1. 0 v rev. 0 | page 20 of 37
data sheet ad9655 rev. 0 | page 21 of 37 ?0.006 ?0.007 ?0.004 ?0.005 ?0.002 ?0.003 0 ?0.001 0.001 0.002 0.003 40 60 80 ?40 ?20 0 20 v ref error (v) temperature (c) internal v ref = 1.4v 12737-056 figure 52. typical v ref drift, v ref = 1.4 v adc r 0.1f 0.1f 2v p-p vcm c c1 1 c1 1 c r 0.1f 0.1f 0.1f 33? 200 ? 33? 33? 33? vinx+ vinx? et1-1-i3 c c 10pf r 1 c1 is optional 12737-057 figure 53. differential double balun input configuration for base band applications 2v p-p r r c1 1 1 c1 is optional 49.9 ? 0.1 f a dt1-1wt 1:1 z ratio vinx? adc vinx+ c1 1 c vcm 33 ? 33 ? 200 ? 0.1f 10pf 12737-058 figure 54. differential transformer coupled configuration for baseband applications
ad9655 data sheet clock input considerations for optimum performance, clock the ad9655 sample clock inputs, clk+ and clk?, with a differential signal. the signal i s typically ac - coupled into the clk+ and clk? pins via a transformer or capacitors. these pins are biased internally (see figure 38 ) and require no external bias. clock input options the ad9655 ha s a flexible clock input structure. the clock input can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal used, clock source jitter is an important consideratio n , as described in the jitter considerations section. figure 55 and figure 56 show two preferred methods for clocking the a d9655 at clock rates up to 1 ghz prior to the internal clock divider . a low jitter clock source is converted from a single - ended signal to a differential si gnal using either a radio frequency ( rf ) transformer or an rf balun. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsms2822 clock input 50? 100? clk? clk+ adc mini-circuits ? adt1-1wt, 1:1 z xfmr 12737-059 figure 55 . transformer coupled differential clock (up to 200 mhz) 0.1f 0.1f 0.1f clock input 0.1f 50? clk? clk+ schottky diodes: hsms2822 adc 12737-060 figure 56 . balun - coupled differential clock (up to 1 ghz) the rf balun configuration is recommended for clock frequencies between 125 mhz and 1 ghz, and the rf transf ormer configuration is recommended for clock frequencies from 2 0 mhz to 200 mhz. the anti parallel schottky diodes across the transformer/balun secondary winding limit clock excursions into the ad9 655 to approximately 0.8 v p - p differential. this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9655 while preserving the fast rise and fall times of the signal that are critical to achieving low jitter performance. however, the diode capacitance comes into play at frequencies above 500 mhz. care must be taken when choosing the appropriate signal limiting diode. if a low jitter clock sou rce is not available, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figu re 57 . the ad9510/ ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 / ad9517 clock drivers , noted a s ad951 x in figu re 57, figure 58 , and figure 59, offer excellent jitter performance. 10 0? 0.1f 0.1f 0.1f 0.1f 240? 240? 50k? 50k? clk? clk+ clock input clock input adc ad951x pecl driver 12737-061 figu re 57 . differential pecl sample clock (up to 1 ghz) a third option is to ac couple a differential lvds signal to the sample clock input pins, as shown in figure 58 . the ad9510/ ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 / ad9517 clock drivers offer excellent jitter performance. 10 0? 0.1f 0.1f 0.1f 0.1f 50k? 50k? clk? clk+ adc clock input clock input ad951x lvds driver 12737-062 figure 58 . differential lvds sample clock (up to 1 ghz) in some applications, it may be acceptable to drive the sample clock inputs with a single - ended 1.8 v cmos signal. in such applications, drive the clk+ pin directly from a cmos gate, and bypass the clk? pin to ground with a 0.1 f capacitor (see figure 59). optional 100? 0.1f 0.1f 0.1f 50? 1 1 50? resistor is optional. clk? clk+ adc v cc 1k? 1k? clock input ad951x cmos driver 12737-063 figure 59 . single - ended 1.8 v cmos input clock (up to 200 mhz ) input clock divider the ad9655 contains an input clock divider that can divide the input clock by integer values from 1 to 8. to achieve a given sample rate, the frequency of the externally applied clock must be multiplied by the divide value. the increased rate of the external clock no rmally results in lower clock jitter, which is beneficial for intermediate frequency ( if ) undersampling applications. rev. 0 | page 22 of 37
data sheet ad9655 clock duty cycle typical high speed adcs use both clock edges to generate a variety o f internal timing signals and, as a result, may be sensitive to the clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad9655 contains a duty cycle stabilizer (dcs) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting t he performance of the ad9655 . noise and distortion performanc e are nearly flat for a wide range of duty cycles with the dcs on . jitter in the rising edge of the clock is still of concern and is no t easily reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates of less than 20 mhz, nominally. the loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. jitter considerations high speed, high resolution adcs are sensitive to the q uality of the clock input. the following equation shows how snr degrades at a given input frequency (f a ) due only to aperture jitter (t j ): snr degradation = 20 log 10 ? ? ? ? ? ? ? ? j a t f 2 1 in this equation, the rms aperture jitter represents the root sum square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter specifications. if under - sampling applications are particularly sensitive to jitter . the effect of jitter alone on snr, with no other noise contributors, is shown in figure 60. 1 10 100 analog input frequency (mhz) 1000 16 bits 14 bits 12 bits 30 40 50 60 70 80 90 100 110 120 130 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 10 bits 8 bits rms clock jitter requirement snr (db) 12737-064 figure 60 . ideal snr vs. analog input frequency and jitter t reat the clock input as an analog signal when apert ure jitter may affect the dynamic range of the ad9655 . separate clock driver p ower supplies from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal controlled oscillators are the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it is recommended that the clock be retime d by the original clock as the last step. see th e an - 501 application note and the an - 756 application note for more infor mation about jitter performance as it r elates to adcs. power dis sipation and power - down mode as shown in figure 61, the power dissipated by the ad9655 is proportional to its sample rate. the ad9655 is placed in power - down mode eith er by t he spi port or by asserting the sdio/ pdwn pin high when in non - spi mode . in this state, the adc t ypically dissipates 2 m w. d u r i ng power - down, the output drivers are placed in a high impedance state. in non - spi mode, a sserti ng the sdio/pdwn pin low returns the ad9655 to its normal operating mode. note that sdio/pdwn is ref erenced to the digital output driver supply (drvdd) and must not exceed that supply voltage. 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30 0.32 20 40 60 80 100 120 total power dissipation (w) sample rate (msps) v ref = 1.4v v ref = 1.0v 12737-065 figure 61 . total power dissipation vs. sample rate ( f sample ) for f in = 9.7 mhz , v ref = 1.0 v and v ref = 1. 4 v the ad9655 a chieve s l ow power dissipation in power - down mode by shutting down the reference, reference buffer, biasing networks, and clock. when using the spi port interface, the user can place the adc in power - down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake - up times are required. d o not invoke s tandby mode while foregro und calibration is in progress . foreground calibration is invoked automatically at power - up, and by executing a digital reset with register 0x08. c ompletion is indicated by the contents of register 0x107 = 0x00. see the memory map section for more details on using these features. rev. 0 | page 23 of 37
ad9655 data sheet digital outputs and timing the ad9655 differential outputs conform to the ansi - 644 lvds standard on default power - up. this default setting can be changed to a low power, reduced signal option (similar to the ieee 1596.3 standard) via the spi. the lvds driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 ma. a 100 ? differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing (or 700 mv p - p differential) at the receiver. when operating in reduced r ange mode, the output current reduces to 2 ma. this re sul ts in a 200 mv swing (or 400 mv p - p differential) across a 100 ? termination at the receiver. the lvds outputs facilitate interfacing with l vds receivers in custom asics and fpgas for superior switching p erformance in noisy environments. single point - to - point net topologies are recommended with a 100 ? termination resistor placed as close as possible to the receiver. t iming errors may result i f there is no far - end receiver termi nation , or if there is poor differential trace routing . to avoid such timing errors, ensure that the trace length is less than 24 inches and that the differential output traces are close together and at equal lengths. figure 62 shows an example of the fco and data stream with proper trace length and position. figure 63 shows the lvds output timing example in reduced range mode. d0 500mv/div d1 500mv/div dco 500mv/div fco 500mv/div 4ns/div 12737-067 figure 62 . lvds output timing example in ansi - 644 mode (default) d0 400mv/div d1 400mv/div dco 400mv/div fco 400mv/div 4ns/div 12737-068 figure 63 . lvds output timin g example in reduced range mode rev. 0 | page 24 of 37
data sheet ad9655 figure 64 . data eye for lvds outputs in ansi - 644 mode with trace lengths of less than 24 inches ( approximate 6 inch trace length result shown ) on standard fr - 4 material, external 100 ? far - end termination only figure 65 . tie jitter histogram for tra ce lengths less than 24 inches ( approximate 6 inch trace length result shown ) figure 64 shows an example of the lvds output data eye us ing the ansi - 644 standar d (default) , and figure 65 shows a time interval error (tie) jitter histogram with trace lengths of less than 24 inches on standard fr - 4 material. figure 66 shows an example of the lvds output data eye using the ansi - 644 standard (default) , and f igure 67 sho ws a time interval error (tie) jitter histogram with trace lengths greater than 24 inches on standard fr - 4 material. note that the tie jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. it is the re spon sibility of the user to determine if the waveforms meet the timing budget of the design. the format of the output data is twos complement by default. see table 11 for an example of the output coding format. to change the output data format to offset binary, see the memory map section. data from each adc is serialized and provided on a separate channel in two lanes in ddr mode. the data rate for each serial stream is equal to (16 bits the sample clock rate)/2 lanes, with a maximum of 1 g bps/lane ( 16 bits 125 msps)/(2 lanes) = 1 g bps/lane ) . the minimum conversion rat e is 2 0 msps. figure 66 . data eye for lvds outputs in ansi - 644 mode with trace lengths greater than 24 inches ( approximate 36 inch trace length result show n) on standard fr - 4 material, external 100 ? far - end termination only f igure 67 . tie jitter histogram for trace lengths greater than 24 inches ( approximate 36 inch trace length result shown ) two output clocks assist in capturing data from the ad9655 . the dco clock s the output data and is equal to 4 the samp le clock (clk) rate for the default mode of operation. data is clocked out of the ad9655 and must be captured on the rising and falling edges of the dco that supports ddr capturing. the fco signal s the start of a new output byte and is equal to the sample clock rate in 1 frame mode. see the timing diagrams section for more information. when the spi is used, the dco phase can be adjusted in approximate ly 60 increments relative to one data cycle (3 0 relative to one dco cycle) . this allows the user to ref ine system timing margins if required. the example dco+ and dco? timing, as shown in figure 2 , is 18 0 relative to one data cycle (9 0 relative to one dco cycle) . in default mode, as shown in figure 2 , the msb is first in the data output serial stream. this can be inverted by using the spi so that the lsb is first in the data output serial stream. rev. 0 | page 25 of 37
ad9655 data sheet table 11 . digital output coding input (v) condition (v) offset binary output mode twos complement mode vin x + ? vin x? + v ref ? 0.5 lsb 1111 1111 1111 11 11 0111 1111 1111 11 11 table 12 . flexible output test modes output test mode bit sequence pattern name digital output word 1 digital output word 2 subject to data format select notes 0000 off (default) not applicable not applicable not applicable 0001 midscale short 12- bit: 1000 0000 0000 not applicable yes offset binary code shown 16- bit: 1000 0000 0000 0000 0010 +full - scale short 12- bit: 1111 1111 1111 not applicable yes offset binary code shown 16- bit: 1111 1111 1111 1111 0011 ? full - scale short 12- bit: 0000 0000 0000 not applicable yes offset binary code shown 16- bit: 0000 0000 0000 0000 0100 checkerboard 12 - bit: 1010 1010 1010 12 - bit: 0101 0101 0101 no 16- bit: 1010 1010 1010 1010 16- bit: 0101 0101 0101 010 1 0101 pn sequence long 1 n ot applicable not applicable yes pn23 itu 0.150 x 23 + x 18 + 1 0110 pn sequence short 1 not applicable not applicable yes pn9 itu 0.150 x 9 + x 5 + 1 0111 o ne - /zero - word toggle 12- bit: 1111 1111 1111 12- bit: 0000 0000 0000 no 16 - bit: 111 1111 1111 1111 16 - bit: 0000 0000 0000 0000 1000 user input register 0x19 and register 0x1a register 0x1b and register 0x1c no 1001 1 - /0 - bit toggle 12- bit: 1010 1010 1010 not applicable no 16- bit: 1010 1010 1010 101 0 1010 1 sync 12- bit: 0000 00 00 1111 not applicable no 16- bit: 0000 000 0 1111 1111 1011 one bit high 12- bit: 1000 0000 0000 not applicable no pattern associated with the external pin 16- bit: 1000 0000 0000 0000 1100 mixed frequency 12- bit: 1010 00 0 1 1001 not applicable no 16- bit: 1010 0001 1001 1100 1 all test mode options except pn sequence short and pn sequence long can support 12 - bit to 16 - bit word lengths to verify data cap ture to the receiver. rev. 0 | page 26 of 37
data sheet ad9655 there are 12 digital output test pattern options available that can be initiated through the spi. this is a useful feature when validating receiver capture and timing. see table 12 for the available output bit sequencing options. some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. note that some patterns do not adhere to the data format select o ption. in addition, custom user defined test patterns can be assigned in register 0x19, register 0x1a, register 0x1b, and register 0x1c. the pseudorandom number ( pn ) sequence short pattern produce s a pseudorandom bit sequence that repeats itself every 2 9 ? 1 or 511 bits. a description of the pn sequence and how it is generated can be found in section 5.1 of the itu - t 0 .150 (05/96) standard. the seed value is all 1s (see table 13 for th e initial values). the output is a parallel representation of the serial pn9 sequence in msb first format. the first output word is the first 16 bits of the pn 9 sequence in msb aligned form. table 13 . pn sequence sequence initial value next three output samples (msb first), twos complement pn sequence short 0x 7f83 0x 5f17 , 0x b209 , 0x ced1 pn sequence long 0x 7 fff 0x 7e00 , 0x 807c , 0x 801f the pn sequence long pattern produces a pseudorandom bit seque nce that repeats itself every 2 23 ? 1 or 8,388,607 bits. a description of the pn sequence and how it is generated can be found in section 5.6 of the itu - t 0 .150 (05/96) standard. the seed value is all 1s (see table 13 f or the initial values) and the ad9655 inverts the bit stream in relation to the itu standard. the output is a parallel representation of the serial pn23 sequence in msb first format. the first output word is the first 16 bits of the pn23 sequence in msb aligned form. see the memory map section for information on how to change these additional digital output timing features through the spi. sdio/ pdwn pin for applications that do not require spi mode operation, th e csb pin is tied to dr vdd, and the sdio/ pdwn pin controls the power - down mode according to table 14. table 14. power - down mode pin settings sdio/pdwn pin voltage device mode a gnd ( d efault) r un device, normal operation dr vdd power down device sclk/dfs pin the sclk/dfs pin is use d for output format selection in applications that do not require spi mode operation. this pin determines the digital output format when the csb pin is held high during device power - up. when sclk/dfs is tied to drvdd, the adc output format is twos c omplement; w hen sclk/dfs is tied to a gnd , the adc output format is o ffset b inary . table 15 . digital output format sclk/ d fs voltage output format agnd offset b inary dr vdd twos c omplement csb pin t ie t he csb pin to dr v dd for applications that do not require spi mode operation. by tying csb high, all sclk and sdio information is ignored. rbias pin to set the internal core bias current of the adc, place a 10.0 k?, 1% tolerance resistor to ground at the rbias pin. output test modes the output test options are described in table 12 and are controlled by the output test mode bits at register 0x0d. when an output test m ode is enabled, the analog section of the adc is disconnected from the digit al back - end blocks and the test pattern is run through the output formatting block. some of the test patterns are subject to output formatting, and some are not. the pn generators from the pn sequence tests can be reset by setting bit 4 or bit 5 of register 0x0d. these tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. for general information, see the an - 877 application note , interfacing to high speed adcs via spi . rev. 0 | page 27 of 37
ad9655 data sheet serial port interfac e (spi) the ad9655 spi allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi offers the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is orga nized into bytes that can be further divi ded into fields, which are docu mented in the memory map section. information specific to the ad9655 is contained in th is data sheet , and takes precedence over the th e an - 877 application note , interfacing to high speed adcs via spi , which provides general information. configuration using the spi three pins define the spi of this adc: the sclk /dfs pin, the sdio /pdwn pin, and the csb pin (see table 16 ). sclk /dfs (a serial clock when csb is low ) synchronize s the read and write data presented from and to the adc. sdio /pdwn (serial data input/output when csb is low ) is a dual - purpose pin that allows data to be sent to and read from the internal adc memory map registers. csb (chip select bar) is an active low co ntrol that enables or disables the spi read and write cycles. table 16 . serial port interface pins pin function sclk /dfs serial clock when csb is low . the serial shift clock input, which synchronize s serial interface reads and writ es. sdio /pdwn serial data input/output when csb is low . a dual - purpose pin that typically serves as an input or an output, depending on the instruction sent and the relative position in the timing frame. csb chip select bar. an active low control that enables the spi mode read and write cycles. the falling edge of csb, in conjunction with the rising edge of sclk /dfs , determines the start of the framing. an example of the seri al timing is shown in figure 68 . see table 7 for definition s of the timing parameters. other modes involving the csb pin are available. csb can be held low indefinitely, which permanently enables spi mode ; this is called streaming. csb can stall high between bytes to allow for additional external timing. when the csb pin is tied high at power - up , spi functions are place d in high impedance mode. this mode turns on the secondary functions of the spi pins . note that, when spi mode is entered, that is, csb is taken low, these secondary functions cannot be invoked without power cycling the device. during the instruction phase of a n spi operation, a 16 - bit instruction is transmitted. data follows the instruction phase, and the length of this data is determined by the w0 and w1 bits ( see figure 68). in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on - chip memory. the first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. if the instruction is a readback operat ion, performing a readback causes the serial data input/output sdio /pdwn p in to change direction from an input to an output at the appropriate point in the serial frame. all data is composed of 8 - bit words. data can be s ent in msb first mode or in lsb first mode. msb first mode is the default on pow er - up and can be changed via the spi port configuration register. for more information about this and other features, see the an - 877 application note , interfacing to high speed adcs via spi . don?t care don?t care don?t care don?t care sdio/pdwn sclk/dfs csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 12737-071 figure 68 . serial port interface timing diagram rev. 0 | page 28 of 37
data sheet ad9655 hardware interface the pins described in table 16 comprise the physical interface between the user programming device and the serial port of the ad9655 . the sclk /dfs pin and the csb pin function as inputs when using the spi interface. the sdio /pdwn pin is bidirec - tional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpg as or microcontrolle rs. one method for spi configuration is described in detail in th e an - 812 application note , micro - controller - based serial port interface (spi) boot circuit . it is recommended that t he spi port not be active during periods when the full dynamic performance of the converter is required. because the sclk /dfs signal, the csb signal, and the sdio /pdwn signal are typically asynchronous to the adc clock, noise from these signals can degrade converter p erformance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9655 to prevent these signals from transitioning a t the converter i nputs during critical sampling periods. the sclk /dfs and sdio /pdwn pins serve a dual function when the spi interface is not in use . when the pins are strapped to drvdd or ground during device power - on, they are associated with a specific function. table 14 and table 15 describe the strappable functions supported on the ad9655 . configuration withou t the spi in applications that do not interface to the spi control registers, the sc lk/dfs pin and the sdio/ pdwn pin serve as standalone cmos - compatible control pins. when the device is powered up, it is assumed that the user intends to use the pins as static control lines for the output data format and po wer - down feature control. in this mode, connect csb to drvdd, which disables the serial port interface. spi accessible featu res table 17 provides a brief descripti on of the general features accessible via the spi. these features are described in general in th e an - 877 application note , interfacing to high speed adcs via spi . the ad9655 device - specific features are described in d etail following table 18 , the external memory map register table. table 17 . features accessible using the spi feature name description power mode allows the user to set either power - down mode or standby mode clock allows the user to access the dcs, set the clock divider, and set the clock divider phase offset allows the user to digitally adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set the output mode output phase al lows the user to set the output clock polarity adc resolution allows power consumption scaling with respect to sample rate rev. 0 | page 29 of 37
ad9655 data sheet memory map reading the memory m ap register table each row in the memory map register table (see table 18 ) has eight bit locations. the memory map is roughly divided into three sections: the chip configuration registers (address 0x00 to address 0x02); the device index register (address 0x05 ); and the global adc function registers, including setup, control, and tes t registers (address 0x08 and beyond ). the memory map registe r table lists the default hexadecimal value for each hexadecimal address shown. the column with the heading bit 7 (msb) contains the most significant bit of the default hexadecimal value given. for example, address 0x05, the device index register, has a he xadecimal default value of 0x33. this means that in address 0x05, bits[7:6] = 00, bits[5:4] = 11, bits[3:2] = 00, and bits[1:0] = 11 (in binary). this setting is the default channel index setting. the default value results in both adc channels receiving th e next write command. for more information on this function and others, see th e an - 877 application note , interfacing to high speed adcs via spi . this application note documents the f unctions contr olled by register 0x00 to register 0xff. s pec ific register functions for the ad9655 are documented in the memory map register descriptions section. open locations all address and bit locations not included in table 18 are not curren tly sup ported for this device. write u nused bits of a valid address location with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x05). if the entire address location is open or not listed in table 18 (for example, address 0x13), this address location must not be written. default values after the ad9655 is soft reset by register 0x00 , critical registers are loaded with default values. the default values for the registers are given in the memory map register table, table 18. logic levels an explanation of logic level terminology is as follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous w ith bit is set to logic 0 or writing logic 0 for the bit. channel specific registers some channel setup functions can be programmed individually for each channel. in these cases, channel address locations are internally duplicated for each channel. the se registers and bits are designated in table 18 as local. these local registers and bits can be accessed by setting the appropriate data channel bits ( chan nel a or channel b) and the clock channel dco bit (bit 5 ) and clock channel fco bit (bit 4) in register 0x05. if all the bits are set, the subsequent write affects the registers of both channels and the dco/fco clock channels. in a read cycle, only set one channel ( channel a or channel b) to read one of the t wo registers. if all the bits are set during a n spi read cycle, the device returns the value for channel a. registers and bits that are designated as globa l in table 18 af fect the entire device and channel features for which independent settings are not allowed between channels. the set - tings in register 0x05 do not affect the global registers and bits. rev. 0 | page 30 of 37
data sheet ad9655 memory map register table the ad9655 uses a 3 - wire interface and 16 - bit addressing ; therefore, bit 0 and bit 7 in register 0x00 are set to 0, and bit 3 and bit 4 are set to 1. when bit 5 in register 0x00 is set high, the spi enters a soft reset, where all of the user registers revert to their default values and bit 2 is automatically cleared. table 18. addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments chip configuration registers 0x00 spi port configuration 0 = sdo active lsb first soft reset 1 = 16 - bit address 1 = 16- bit address soft reset lsb first 0 = sdo active 0x18 n ibbles are mirrored to allow a given register value to perform the same function for eit her msb first or lsb first mode . 0x01 chip id (global) 8 - bit chip id, bits[7:0] 0x c 2 = ad9655 , dual , 16- bit , 125 msps , serial lvds 0x c2 unique chip id used to differentiate devices; read only. 0x02 chip grade (global) open speed grade id , bits [6:4] 110 = 125 msps revision, bits[3:0] 0x 62 unique speed grade id used to differentiate graded devices; r ead only. dev ice index register 0x05 device index open clock channel dco clock channel fco open data channel b data channel a 0x33 bits are set to determine which device on chip receives the next write command. default is all devices on chip. global adc function registers 0x08 power modes (global) open power mode 00 = chip run 01 = full power - down 10 = standby 11 = digital reset 0x00 determines various generic modes of chip operation. 0x09 clock (global) open dcs b ypass 0 = inactive 1 = active open dcs 0 = off 1 = on 0x0 4 dcs control s . bit 2 = 1 bypasses the clock divider as well as dcs . 0x0b clock divide (global) open clock divide ratio , bits [2:0] 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 s etting register 0x09 , bit 2 = 1 bypasses the clock divider as well as dcs . 0x0c enhancement control open chop mode 0 = off 1 = on open 0x00 enables/ disables chop mode. rev. 0 | page 31 of 37
ad9655 data sheet addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments 0x0d test mode (local except for pn sequence resets) user input test mode 00 = single 01 = alternate 10 = single once 11 = alternate once ( bit s [7:6] affect user input , test mode only, bits[3:0] = 1000) reset pn long gen - erator reset pn short gen erator output test mode, bits[3:0] (local) 0000 = off (default) 0001 = midscale short 0010 = positive fs 0011 = negative fs 0100 = alternating checkerboard 0101 = pn23 sequence 0110 = pn9 sequence 0111 = one - /zero - word toggle 1000 = user input 1001 = 1 - /0 - bit toggle 1010 = 1 sync 1011 = one bit high 1100 = mixed bit frequency 0x00 when set, the test data is placed on the output pins in place of normal data. 0x10 offset adjust (local) 8 - bit device offset adjustment, bits[7:0] (local) ; o ffset adjust in lsbs from ?128 to +127 (twos complement format) 0x00 device offset trim. 0x14 output mode 0 lvds - ansi/ lvds - ieee option 0 = lvds - ansi 1 = lvds - ieee reduced range link (global); see table 19 0 0 0 output invert (local) open output format 0 = offset binary 1 = twos comple - ment (global) 0x01 configures the outputs and format of the data. 0x16 output phase open input clock phase adjust, bits[6:4] (value is number of input clock cycles of phase delay ); see table 20 output clock phase adjust, bits[3:0] (0000 through 10 11); see table 21 0x03 on devices using global clock divide, bits[6:4] determine which phase of the divider output supplies the output clock. internal latchi ng is unaffected. 0x18 v ref open internal v ref adjustment digital sc aling , bits[2:0] 000 = 1.0 v p - p (1.4 v p - p) 001 = 1.14 v p - p (1.6 v p - p) 010 = 1.33 v p - p (1.86 v p - p) 011 = 1.6 v p - p (2.24 v p - p) 100 = 2.0 v p - p (2.8 v p - p) 0x04 d igitally adjusts full - scale input voltage. does not affect analog input swing. v alues shown are for v ref = 1.0 v (1.4 v) . 0x19 user_patt1_lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined pattern 1 (8 lsb s) . 0x1a user_patt1_msb (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined pattern 1 (8 msb s) . 0x1b user_patt2_lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined pattern 2 (8 lsb s) . 0x1c user_patt2_msb (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined pattern 2 (8 msb s) . rev. 0 | page 32 of 37
data sheet ad9655 addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments 0x21 serial output data control (global) lvds output 0 = m sb first (default) 1 = lsb first sdr/ddr one - lane/two - lane, bitwise/bytewise, bits[6:4] 000 = sdr two - lane, bitwise 001 = sdr two - lane, bytewise 010 = ddr two - lane, bitwise 011 = ddr two - lane, bytewise (default) 100 = ddr one - lane, wordwise 0 0 = 1 frame (default) 1 = 2 frame serial output number of bits 00 = 16 bits (default) 01 = 14 bits 10 = 12 bits 1 1 = 1 0 bits 0x30 serial stream control. 0x22 serial channel status (local) open channel output reset channel power - down 0x00 used with register 0x05 to powe r down individual sections of a converter. 0x101 user i nput /o utput control 2 open disable sdio pull - down 0x00 disables sdio pull - down resistor . 0x102 user i nput /o utput control 3 open vcm power - down 0 0 0 0x00 vcm control. 0x107 foreground calibrations s tatus open bit 1 = 1 during foreground calibration , bit 1 = 0 after calibration is complete bit 0 = 1 during foreground calibration , bit 0 = 0 after calibration is complete 0x00 read only. 0x112 cl oc k monitor control open 0 recovery mode 000 = r ecovery off (default) 101 = recovery on 1 1 1 0x07 select clock recovery mode . 0x114 v ref control open drive v ref e xternal 0 = n o 1 = y es v ref 00 = 1.0 v 01 = 1.2 v 10 = 1.3 v 11 = 1.4 v 0x00 bits[1:0] set the internal reference voltage. bit 2 disables the reference if an external source is desired . rev. 0 | page 33 of 37
ad9655 data sheet memory map register descriptions for general information about the functions controlled in register 0x00 to register 0xff, see th e an - 877 application note , interfacing to high speed adcs via spi . device index (register 0x05) there are certain features in the map that can be set indepen - dently for each channel, whereas other features apply globally to all channe ls (depending o n context), regardless of which channel is selected . bits[1:0] in register 0x05 can be used to select which individual data cha nnel is affected by the next spi action . the output clock channels can be selected in register 0x05 , as well. a smaller subset of the independent feature list can be app lied to those devices. refer to the following sequence of spi writes for an example of how to use register 0x5 to power do wn channe l b while keeping cha nnel a active: 1. spi_write (0x0 5 , 0x0 2 ) d esignates channel b to be affected by the next local spi register instruction . 2. spi_wri te (0x 22 , 0x0 1 ) power s down the channel previously designated . 3. spi_write (0x 05 , 0x 31) designates dco, fco and channel a to be affected by future local spi register instruction (optional) . 4. spi_write (0x08, 0x03) digital reset . 5. spi_write (0x08, 0x0 0 ) takes the device back to normal operation . power modes (register 0x08) bits[7:2 ] open bits[1:0] power mode in normal operation (bits[1:0] = 00), both adc channels are active. in power - down mode (bits[1:0] = 01), the digital datapath clocks are disabled while the digital datapath is reset. outputs are disabled. in standby mode (bits[1:0] = 10), the digital datapath clocks and the outputs are disabled. do not invoke s tandby mode while foreground calibration is in progress . foreground calibration is in voked automatically at power - up and by executing a digital reset with register 0x08. foreground calibration completion is indica ted by the contents of register 0x107 = 0x00. during a digital reset (bits[1:0] = 11), a foreground calibration is invoked, all the digital datapath clocks and the outputs (where applicable) on the chip are reset, except the spi port. note that the spi is always left under control of the user; that is, it is never automatically disabled or in reset (except by power - on reset). enhancement control (register 0x0c) bits[7:3] open bit 2 chop mode for applications sensitive to offset voltages and other low frequency noise, such as homodyne or direct conversion receivers, chopping in the first stage of the ad9655 is a n available feature, enabled by setting bit 2. in the frequency do main, chopping translates offsets and other low frequency noise to f clk /2, where it can be filtered. bits[1:0] open output mode (register 0x14) bit 7 0 bit 6 lvds - ansi/lvds - ieee option setting this bit selects the lvds - ieee (reduc ed range) option. the default setting is lvds - ansi. when lvds - ansi or the lvds - ieee reduced range link is selected , t he driver current is automatically selected to give the proper output swing. table 19 . lvds - ansi/lvds - ieee options output mode, bit 6 output mode output driver current 0 lvds - ansi automatically selected to give proper swing 1 lvds - ieee reduced range link automatically selected to give proper swing bits[5:3] 000 bit 2 output invert setting this bit inverts the output bit stream. bit 1 open bit 0 output format by default, this bit is set to send the data output in twos complement format . clearing this bit to 0 changes the output mode to offset binary. rev. 0 | page 34 of 37
data sheet ad9655 output phase (register 0x16) bit 7 open bits[ 6:4] input clock phase adjust when the clock divider (register 0x0b) is used, the applied clock is at a higher frequency than the internal sampling clock. bits[6:4] determine at which phase of the external clock sampling occurs. this is applicable only whe n the clock divider is used. selecting a value for bits[6:4] greater than register 0x0b , bits[2:0] is prohibited. see table 20 for details. table 20 . input clock phase adjust options input clock phase adjust, bits[6:4] number of input clock cycles of phase delay 000 (default) 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 bits[3:0] output clock phase adjust see table 21 for details. table 21 . output clock phase adjust options output clock (dco), phase adjust, bits[3:0] dco phase adjustment ( approximat e degrees relative to the d0x/d1x edge) 0000 0 0001 60 0010 120 0011 (default) 180 0100 240 0101 300 0110 360 0111 420 1000 480 1001 540 1010 600 1011 through 1111 660 serial output data control (register 0x21) the serial output data control register to program s the ad9655 in various output data modes, depending on the data capture solution. table 22 describes the various serialization options available in the ad9655 . note that , in single data rate (sdr) mode, the dco frequency is double that of the frequency in ddr mode for a given sam ple rate . in sdr mode, to stay within the capability of the dco lvds driver, the adc sample rate must be reduced to 62.5 msps to keep the dco frequency at 500 mhz. user i/o control 2 (register 0x101) bits[7:1] open bit 0 disable sdio pull- down bit 0 can be set to disable the in ternal 3 1 k pull - down resistor on the sdio /pwdn pin, which limit s the loading w hen many devices are connected to the spi bus. user i/o control 3 (register 0x102) bits[7:4] open bit 3 vcm power - down bit 3 can be set high to pow er down the internal vcm generator. this feat ure is used when applying an external reference. bits[2:0] 0 00 clock monitor control (register 0x1 1 2) bit 7 open bit 6 0 (reserved) bits[ 5 :3] recovery mode by default (bits[ 5 :3] = 000 ) , r ecovery mode is off . in this condition, t he ad9655 does not automatically recover from a state change or corruption due to a clock glitch or irregularity. with recovery mode off, a digital res et (register 0x08 = 0x03, then register 0x08 = 0x00) is needed to restore the ad9655 to proper operation in case of disruption due to clock instability . with clock recovery mode on (bits[ 5 :3] = 10 1 ) , ad9655 automatically recover s from corruption due to a clock glitch or irregularity. after the corruption is auto detected , 31 10 6 clock c ycles are needed to restore proper operation. bits[ 2:0] recovery mode setup recover y mode is set up for correct op eration by default (bits[2:0] = 111 ). v ref control (register 0x1 14) this register adjusts the internal analog v ref value. a digital reset using register 0x08 must follow any change in analog v ref . table 22 . spi register 0x21 options serialization options selected register 0x21 contents serial output number of bits (sonb) frame mode serial data mode dco multiplier timing diagram 0x30 16- bit 1 ddr two - lane bytewise 4 f s see figure 2 (default setting) 0x20 16 - bit 1 ddr two - lane bitwise 4 f s see figure 2 0x10 16- bit 1 sdr two - lane bytewise 8 f s see figure 2 0x00 16- bit 1 sdr two - lane bitwise 8 f s see figure 2 0x40 16- bit 1 ddr one - lane wordwise 8 f s see figure 3 rev. 0 | page 35 of 37
ad9655 data sheet rev. 0 | page 36 of 37 applications information design guidelines before starting design and layout of the ad9655 as a system, it is recommended that the designer become familiar with these guidelines, which describe the special circuit connections and layout requirements needed for certain pins. power and ground guidelines when connecting power to the ad9655 , it is recommended that two separate 1.8 v supplies be used. use one supply for analog (avdd); use a separate supply for the digital outputs (drvdd). for both avdd and drvdd, use several different bypass capacitor values to cover both high and low frequencies. place these capacitors close to the point of entry at the pcb level and close to the pins of the device, with minimal trace length. a single pcb ground plane is sufficient when using the ad9655 . with proper bypassing and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. clock stability considerations when powered on, the ad9655 enters an initialization phase during which an internal state machine sets up the biases and the registers for proper operation. during the initialization process, the ad9655 needs a stable clock. if the adc clock source is not present or not stable during adc power-up, it disrupts the state machine and causes the adc to start up in an unknown state. to correct this, reinvoke an initialization sequence after the adc clock is stable by issuing a digital reset via register 0x08. in the default configuration (internal v ref , ac- coupled input) where v ref and v cm are supplied by the adc, a stable clock during power-up is sufficient. whenv cm is supplied by an external source, this, too, must be stable at power-up; otherwise, a subsequent digital reset via register 0x08 is needed. clock instability during normal operation may also necessitate digital reset to restore proper operation. the pseudo code sequence for a digital reset is as follows: 1. spi_write (0x08, 0x03)digital reset. 2. spi_write (0x08, 0x00)normal operation. exposed pad thermal heat slug recommendations it is required that the exposed pad on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance of the ad9655 . it is recommended that an exposed continuous copper plane on the pcb mate to the ad9655 exposed pad, pin 0. it is also recommended that this copper plane have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. solder-fill or plug these vias. to maximize the coverage and adhesion between the adc and pcb, partition the continuous copper plane by overlaying a silkscreen or solder mask on the pcb into several uniform sections. this provides several tie points between the adc and pcb during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. see figure 69 for a pcb layout example. for detailed information on packaging and the pcb layout of chip scale packages, see the an-772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) . silkscreen partition pin 1 indicator 12737-072 figure 69. typical pcb layout vcm bypass the vcm pin to ground with a 0.1 f capacitor. reference bypassing externally bypass the vref pin to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. spi port the spi port must not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9655 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
data sheet ad9655 outline dimensions 08-16-2010-b 1 0.50 bsc bot t om view top view pin 1 indic a t or 32 9 16 17 24 25 8 exposed pa d pin 1 indic a t or sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min * 3.75 3.60 sq 3.55 * compliant to jedec standards mo-220- whhd-5 with the exception of the exposed pad dimension. figure 70 . 32 - lead lead fram e chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp - 32 - 12) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9655 bcpz -125 ? 40c to +85c 32- lead lead frame chip scale package (lfcsp_wq) cp -32-12 ad9655 bcpzrl7 - 125 ? 40c to +85c 32- lead lead frame chip scale package (lfcsp_wq) cp -32-12 ad9655 - 125ebz evaluation board 1 z = rohs compliant part. ? 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12737 - 0 - 1/15(0) rev. 0 | page 37 of 37

▲Up To Search▲

Price & Availability of AD9655-125EBZ

	To Download AD9655-125EBZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .